1. Field of the Invention
The present invention relates to a semiconductor memory and a fabricating method thereof, in particular to a dynamic random access memory and a method thereof.
2. Description of the Related Art
An SOC (System on a Chip) device technique has been expected as the technique capable of remarkably enhancing the performance of an LSI system. This technique opens up new possibilities for reaching the world which could not be achieved by a system of discrete LSI chips in combination. For example, power consumption can be remarkably reduced or prodigious data-transfer ability can be achieved by equipping one chip with a large-capacity memory device and a logic device. In particular, a dynamic random access memory (DRAM) hybrid logic device has been developed all over the place in view of its market scale. In order to establish the business of the DRAM hybrid logic device together with technical possibility, it is important to form the device at a proper cost.
Based on such a concept, IEDM 99, pp. 45-48 discloses the structure and process for fabricating the device (refer to FIGS. 7 and 8 in the present specification).
In this technique, silicide technique of CoSi2 (cobalt silicide) used in a logic unit is introduced also in a memory cell for a DRAM. The structures of transistors in a memory cell unit and the logic unit become identical to each other by using CoSi2 also in the memory cell. Consequently, it is unnecessary to use a special (additional) process required in the case where the transistors are constituted of different structures, thus preventing any increase in the number of processes.
However, the process for forming a DRAM cell is an additional one with respect to the process for forming only a logic device. Therefore, it is important to eliminate the process for forming the DRAM cell from the viewpoint of the reduction of the number of processes.
In the related art, the process for forming all constituent elements is used for forming the DRAM cell. That is, the process includes the process for forming a capacitor contact constituting the capacitor of a memory cell and a cylinder (an accumulation electrode).
In this manner, the fabrication of the capacitor contact and the cylinder by two kinds (two processes) of mask works is caused by, in particular, the plane layout and fabricating processes of the memory cell.
First of all, explanation will be made below on the plane layout of the DRAM cell in the related art. FIG. 8 illustrates the plane layout of the DRAM cell in the related art. In the same manner, FIG. 7 is a cross-sectional view showing mainly a capacitor plate (an opposite electrode) and a bit line, taken along a line C-Cxe2x80x2 of FIG. 8 illustrating the plane layout.
As shown in FIG. 8, all of the intervals between bit line contacts 317 formed on one bit line 319 are fixed, bit line contacts formed on an adjacent bit line are arrayed in such a manner that a contact formed on the adjacent bit line is located at a position just half of the interval between the bit line contacts. This may be referred to as the array of a half pitch.
In this layout, the memory cell is laid out in such a manner as to increase the size of the cylinder as possible since the size of the cylinder is proportional to the cell capacity. As for a cylinder opening 312 and a capacitor contact 313 illustrated in FIG. 8, the interval between adjacent cylinders is great in a longitudinal direction of the bit line 319 but is small in a direction perpendicular to the bit line 319. The adjacent capacitor contact 313 is located between word lines 304 (gate electrodes 204 in FIG. 7). The cylinder openings 312 are laid out in different dimensions in X and Y directions in such a manner as to extend above the word line 304 (the gate electrode 204 in FIG. 7) in order to enlarge the size in the direction in which the interval between the cylinders is greater.
FIG. 7 is the cross-sectional view showing the memory cell, in which there are used 200""s reference numerals corresponding to 300""s reference numerals used in the plan view of FIG. 8.
The gate electrode 204 and impurity diffusion layers 206 and 207, constituting a memory cell transistor, are formed on a silicon substrate 201. A capacitor plate 216 is formed via an accumulation electrode 214 and a capacitor insulating film 215 constituting a capacitor of the memory cell. Furthermore, a bit line contact 217 for writing or reading data in or out of the memory cell is connected to the memory cell transistor and the bit line 319 illustrated in FIG. 8, and therefore, is opened through a first inter layer film 210 and a second interlayer film 211.
Next, a description will be given of the process for fabricating the memory cell in there late dart. Although a layout is different, processes to a process for forming the gate electrode and a stopper nitride film are the same as those in embodiments according to the present invention, and therefore, their description will be omitted here (see the description in the embodiments). The sequentially fabricating processes are illustrated in FIGS. 9A to 9D.
First of all, as illustrated in FIG. 9A, after formation of as topper nitride film, a BPSG film is formed, thereby obtaining the first interlayer film 210. Subsequently, photolithography is carried out, thereby obtaining a resist 222, followed by the etching by the use of a resist 222 as a mask, whereby the capacitor contact 213 is opened.
Thereafter, polycrystalline silicon doped with impurities is grown over the entire surface, followed by etching back by dry etching, thereby forming a capacitor contact plug 233, as illustrated in FIG. 9B. Furthermore, a BPSG film is formed, thus obtaining the second interlayer film 211. And then, the second interlayer film 211 is subjected to photolithography and dry etching, thereby shaping a resist 242 and the cylinder opening 212.
Moreover, as illustrated in FIG. 9C, HSG silicon doped with impurities is deposited on the cylinder opening 212 and the second interlayer film 211, there by obtaining an accumulation electrode material 214a. Subsequently, the cylinder opening 212 covered with the accumulation electrode material 214a is filled with a resist 262.
In this state, the accumulation electrode material 214a is etched back so as to obtain an accumulation electrode 214 with the accumulation electrode material 214a remaining only inside of the cylinder opening 212. Subsequently, as illustrated in FIG. 9D, the capacitor insulating film 215 made of Ta2O5 (tantalum oxide) is formed on the accumulation electrode 214. Furthermore, TiN (titanium nitride) and polycrystalline silicon doped with impurities are laminated in sequence.
Thereafter, the capacitor plate 216 illustrated in FIG. 9D is formed by photolithography and dry etching. Moreover, there is formed a third interlayer film 221 covering the capacitor plate 216, and then, the bit line contact 217 is formed by photolithography and dry etching. In this state, a film is formed of Ti (titanium) and TiN, and then, tungsten is embedded into the bit line contact, thereby obtaining a bit line plug 218 illustrated in FIG. 7. Subsequently, a film is formed of TiN, thereby obtaining a bit line 219 illustrated in FIG. 7 also by photolithography and dry etching. Thereafter, a fourth interlayer film 222 is formed, thus obtaining the memory cell in the related art.
The layout of the memory cell and the method for fabricating the capacitor contact for the memory cell have been described above. The layout of the memory cell experiences a problem as follows.
The cylinder for the capacitor is laid out in as large a size as possible, and further, the capacitor contact is as compactly laid out as possible in such a manner as to be inserted between the word lines (the gate electrodes): that is, both of the cylinder and the capacitor contact are laid out on the utterly different concepts, and as a result, there still remains plenty of room for reduction of the cell size.
Additionally, the method for fabricating the capacitor contact for the memory cell experiences a problem as follows.
It is important to reduce the number of fabricating processes in order to reduce a cost. However, the capacitor contact (designated by reference numeral 213 in FIG. 7 and reference numeral 313 in FIG. 8) and the cylinder opening (designated by reference numeral 212 in FIG. 7 and reference numeral 312 in FIG. 8) constituting the capacitor for the memory cell are formed in the independent processes in the related art, thus inducing an increase in the number of fabricating processes.
As described above, it has been indispensable in the layout used in the related art to constitute the capacitor contact and the cylinder in the two kinds of mask works.
In other words, since the function and structure of the capacitor contact are normally different from those of the cylinder (an accumulation electrode forming region), the two kinds of mask works (or two kinds of mask layers) are used. As is seen from the plane layout of the memory cell in the related art as illustrated in FIG. 8, the cylinder (the cylinder opening 312) and the capacitor contact are not formed into the same shape as each other, and further, are different in positional relationship. Consequently, the cylinder and the capacitor contact cannot be formed by using one and the same mask.
An object of the present invention is to provide a semiconductor device and a fabricating method thereof in which the number of processes of fabricating a DRAM cell and the area of a memory cell can be reduced.
A semiconductor device of the present invention includes,
a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric film, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening, the lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate, and a conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.
A semiconductor device of the present invention includes:
a semiconductor substrate, a plurality of bit lines formed over the semiconductor substrate arranged in a first direction in that order, each of bit lines extending in a second direction substantially perpendicular to the first direction, a plurality of bit line contacts connected to the respective bit lines and the semiconductor substrate, and a plurality of capacitor contacts connected to the semiconductor substrate, wherein a first bit line contact of the bit line contacts connected to a first bit line of the bit lines and a second bit line contact of the bit line contacts connected to a second bit line of the bit lines are arranged at a line extending in the first direction, the capacitor contacts are arranged at the line.
A method of forming a semiconductor device of the present invention comprising:
forming a first interlayer insulating film on the semiconductor substrate;
forming a second interlayer insulating film on the first interlayer insulating film;
forming a first contact hole through the second interlayer insulating film to expose surface of the first interlayer insulating film;
forming a second contact hole through the first interlayer insulating film to expose surface of the semiconductor substrate and being connected to the first contact hole; and
forming a conductive film covering at least the exposed surface of the semiconductor substrate and the side walls of the first and second interlayer insulating films exposed by the first and second contact hole;
wherein the second contact hole is formed into such a shape that diameter of the first contact hole reduces gradually from the second contact hole toward the semiconductor substrate.